TPUv4 Adds Large On-Chip Memory

The TPUv4 is now generally available through Google Cloud, although the company has used it internally for a year. The ASIC doubles the number of matrix units relative to the TPUv3.
21Nov

Apple Watch Series 8 Teardown

In the ever-evolving world of wearable technology, Apple has consistently pushed the boundaries of innovation. Their latest offering, the Apple Watch Series 8 A2771, is no exception. Packed with cutting-edge features and impressive hardware, this watch promises to redefine what we can expect from a smartwatch.
18Nov

It’s cold and foggy…

It’s cold and foggy… Shereen Vaux Order activity for semiconductor equipment extended its decline, slipping one point to 62 degrees Subcons/Advanced packaging was the only segment to increase last week which could be signaling a turn around in business sentiment All other segments declined with
16Nov

A Trip Down TSMC Memory Lane – Part 1

Logic Blog A Trip Down TSMC Memory Lane – Part 1 Dick James A few months ago we published a blog on MOS process history, triggered by Pat Gelsinger’s keynote at the Intel Innovation Days in November last year, and while at the start it was generic, when we got to 90 nm we became specific and showed
15Nov

Webinar: Hybrid bonding technology - today and tomorrow

TechInsights experts review applications of hybrid bonding technology, and discuss what’s to come. This presentation compiles content from TechInsights’ subject matter experts in Memory, Image Sensor, and Logic, and from Engineers specializing in a variety of reverse engineering techniques.
15Nov