AMD Expands 5G RFSoC Portfolio

Obtained through its Xilinx acquisition, AMD’s RFSoCs meld FPGA and processor functions with blocks for mobile infrastructure. The ZU64DR and ZU63DR join a line of RFSoCs that implement DFE functions.

Joseph Byrne

AMD is scaling down the Zynq RFSoC digital-front-end (DFE) products it launched in 2021 to address low-cost 5G radios. Due to ship in May, the ZU63DR still has low-PHY functions but reduces the number of transmit and receive paths to four (4T4R). The ZU64DR supports 8T8R but excludes the low PHY.

AMD obtained the RFSoC product line through its acquisition of Xilinx. They build on the latter company’s Zynq chips—which integrate a processor subsystem with an FPGA—by adding ADCs and DACs, optional soft-decision forward-error-correction (SD-FEC) blocks, and other functions that mobile-infrastructure radios need.

Following the third RFSoC generation, Xilinx developed the RFSoC DFE family. This line integrates hard DFE functions such as digital predistortion and crest-factor reduction, shrinking the associated die area and power as well as increasing performance. The initial family members also integrate low-PHY functions to support the Option 7 split favored by the O-RAN Alliance and others.

Omitting the low PHY, the ZU64DR targets Option 8 deployments, which keep PHY functions in the base station like traditional radio access networks (RANs) do. The new RFSoC still benefits from the hard DFE and is similar to the earlier ZU67DR. It targets both single 8T8R MIMO radios and, for lower-cost macrocells, three-sector 2T2R radios.

The ZU63DR reduces cost relative to the earlier ZU65DR, a 6T6R chip that can serve millimeter-wave (mmWave) designs. It operates as an intermediate-frequency transceiver and integrates a mmWave DFE. The new design’s 4T4R, DFE, and low-PHY capabilities target 4T4R and dual-band 2T2R Option 8 radios, which serve in low-cost RANs.