Samsung and TSMC Head for 2 nm

Samsung and TSMC are forging ahead with 3 nm and 2 nm silicon processing as well as 3D-packaging technologies. Globally dispersed fab construction continues for old and new nodes.

Dick James

Having put 3 nm processes into production, Samsung and TSMC are marching inexorably toward the 2 nm node in 2025; backside power should appear a year later. Advanced packaging also figures prominently in their plans.

Samsung already has gate-all-around technology in limited production, while it is emerging in TSMC’s 2 nm generation. Both companies plan variants at each node level to target higher performance, lower power, or lower cost.

Various 2.5D and 3D packaging options will continue to proliferate as advanced packaging moves towards higher performance and lower cost, making it accessible to more designers. TSMC is further ahead in the heterogeneous integration race, but Samsung arguably has an advantage in memory-hungry AI products because of its background in high-bandwidth memory (HBM) manufacture.

In their newer packaging approaches, both companies are promoting their alliances, which combine entities from across the semiconductor landscape to ensure no supply-chain bottlenecks form. Whether it’s data for chip designers or handlers for testers, all contributors must ensure their piece of the flow is ready for volume production.

Both companies are expanding their capacity to support the new process nodes and to broaden their global footprints. Economic questions notwithstanding, fab construction continues in earnest to put recent shortages into the rearview mirror, including older nodes such as 28 nm.