Graphcore Shows More WoW at ISSCC

Graphcore has revealed how it hybrid bonds a deep-trench-capacitor die and AI accelerator, describing manufacturing techniques and a voltage-swing reduction. A Shmoo plot shows how adding the capacitor die can cut power or boost the clock rate.

 

Dick James

 

Just as a cycling air conditioner causes voltage to sag, dimming nearby incandescent lights, activating a transistor causes a momentary droop on a chip’s power rail. A single transistor’s effect is small, but the cumulative effect is large for billions at once.

Graphcore faced this problem with its Colossus Mk2 GC200 chip. Integrating 1,472 cores that crunch floating-point operations in parallel, it switches billions of transistors at a time. Employing bulk-synchronous-parallel (BSP) computation exacerbates the problem by synchronizing cores’ data-exchange and computation phases.

To mitigate the problem, the well-funded AI startup applied TSMC’s wafer-on-wafer (WoW) technology. It bonds a die comprising an array of capacitors to a new die based on the GC200: the Mk2x. Called Bow, the new product clocks 40% faster or reduces power by 20% at the same speed.

At ISSCC, the company disclosed additional design details, including images of its Mk2x “intelligence-processing unit” (IPU) and its deep-trench-capacitor (DTC) die. Comparisons between the accelerator with and without an attached DTC quantify voltage transients and frequency gains.