Chiplet Technology Advances

Packaging technology goes hand in hand with chiplets. Examples include basic PCB-based 2D structures, passive silicon interposers and bridges for 2.5D packages, 3D packages employing active interposers, and hybrid bonding.

 

Dick James

 

The cost and complexity of multichip packaging have always been a challenge, but the situation has worsened. Advanced processes are no longer leading to cheaper chips. Separating functions and technology nodes into different die, however, can achieve system-level cost, space, and performance benefits at a lower expense than huge chips in leading-edge process technologies.

Chiplets, the embodiment of this idea, have become a hot topic in recent years, making enough waves to motivate the first Chiplets Summit. They’ve even appeared in high-performance computing (HPC): AMD and Intel have trumpeted their use in the Frontier and Aurora supercomputers.

Packaging chiplets is more expensive than packaging single die, but countervailing factors include the lower cost of smaller die, the ability to mix technology generations to reduce cost, and the tendency for larger and more-complex chips to exceed the lithography reticle limit of about 860 mm2. But the ultimate driver is the need for more performance. The challenge is to ensure that the cost/benefit calculation is positive.

Chiplet-packaging technology and techniques have evolved into an array of options whose value depends on a chip assembly’s cost and performance requirements. Packaging analysis of some initial products employing chiplets provides a view of those options.