Sony ISP from 1.12 μm Pixel Pitch, 12 MP, Stacked Back-Illuminated CMOS Image Sensor Standard Floorplan Analysis
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This is a Standard Floorplan Analysis (FAR) of the image signal processor (ISP) die from the 12 MP, 1.12 μm pixel pitch, stacked back-illuminated CMOS image sensor (CIS) extracted from the Apple iPhone 15 Pro Max rear-facing periscope telephoto camera. The ISP die is fabricated using six copper metal interconnect layers, one aluminum layer, and one copper layer for the hybrid bond (direct bond interconnect (DBI)), tungsten (W) contacts, high-k metal gate (HKMG) transistors, and shallow trench isolation (STI). The minimum observed metal and contacted gate pitches are 85 nm and 120 nm, respectively. These measured critical dimensions, along with the observed features of the transistors, suggest that the ISP functionality was manufactured using TSMC 22 nm technology.
