TechInsights finally found 3D Xtacking® NAND devices manufactured from Yangtze Memory Technologies Co., Ltd. (YMTC) in Wuhan, China. With this device, YMTC has become China's first mass-producer of 3D NAND flash memory chips.

This 64L 3D NAND flash device represents the first major competitive semiconductor product to come out of China’s state-backed investment in cutting-edge memory chips. There is no question that this will disrupt the 52 billion dollar NAND memory market and its respective market leaders Samsung, Kioxia, Western Digital, Micron, Intel, and SK hynix.

YMTC’s 64L 3D NAND device is a disruptor not only because it is offered by a significant new entrant, but because of its Xtacking architecture.

TechInsights’ early analysis of YMTC 3D 64L Xtacking TLC NAND devices, found in the UNIC Memory Secure S1-C 64 GB USB, shows 73 gates in total for a vertical NAND string with nine vertical channel (VC) holes including one dummy hole between common source line contacts. It is likely that 4 select gates (1 GST and 3 SSTs) and 5 dummy gates are also used.

Due to Xtacking architecture in which periphery circuits and memory cell operations are processed on a separate wafer, the array efficiency and memory bit density are considerably higher than conventional 3D NAND such as Samsung 64L V-NAND and KIOXIA/WD 64L BiCS NAND. For example, YMTC 64L 256 Gb die bit density is 4.41 Gb/mm² which is higher than Samsung 64L 256 Gb die (3.42 Gb/mm²), and comparable to Micron/Intel 64L CuA FG 256 Gb TLC die (4.40 Gb/mm²) The NAND memory array efficiency on the die for YMTC 64L shows more than 90 %.

We confirmed their Xtacking with two different dies for logic and memory array separately, which means each die has its own unique die markings.

Since YMTC Xtacking uses Wafer-to-Wafer bonding technology, the NAND array is upside-down on periphery circuits. The process integration consists as (1) Metal 1 through Metal 4 for periphery circuits on a wafer, (2) NAND array with a source plate (SP) and Metal 1’ through Metal 3’ on a separate wafer, (3) Wafer-to-Wafer bonding to connect M4 and Metal 3’, (4) Through SP Via and Metal 5. Here, Metal 1’ is for BL. NAND array die substrate is very thin comparing with peripheral circuitry die due to a thinning process after hybrid-bonding.

NAND array consists of the same number of total gates compared to KIOXIA/WDC BiCS 64L 3D NAND. Bit-line half pitch for the device is 20 nm, which means they use a double patterning technology (DPT) likely with self-aligned double patterning (SADP). They do not use any type of metal straps to connect bit lines with NAND channels, which is different from Samsung’s 64L V-NAND array structure. Top select gate (TSG) cut process is also used on array.

We found some unique and very innovative technologies used on YMTC 64L 3D NAND integration such as TSC (Through Silicon Contact) or TSV (Through Silicon Via) through silicon source plate, TAC (Through Array Contact) for memory core interconnection, and Hybrid Cu-to-Cu bonding technology as well.

TechInsights has considerable analysis underway for this part. So far, we have planned the following analysis:

• Floorplan – Top metal and polysilicon planar die image, SEM X-section, process proof, floorplan analysis and die utilization including block sizes and functionality, die and package cost
• Peripheral design - Plan view SEM image set with hierarchical schematics of target blocks
• Structural and materials - SEM planar and X-sections, TEM EDS and EELS, SCM, SIMS and other advanced techniques of structural and material analysis
• Process flow - Process flow steps and 3D emulations of advanced semiconductor technologies.
• Circuit Reverse Engineering - Hierarchical schematics demonstrate the design from the block down to gate level - all linked to the original layout, showing the extracted gates and associated interconnects.

TechInsights Memory subscribers are able to view our work in progress as we analyze this product further, and will have access to full reports as they publish.

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