MediaTek Dimensity 9300 (N4P) Transistor Characterization
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This report presents key DC electrical characteristics for logic NMOS and PMOS transistors located in the CPU1 region of the MediaTek AHJ11236C die found inside the MediaTek MT6989W Dimensity 9300 application processor.
The MediaTek MT6989W Dimensity 9300 application processor was extracted from the Vivo X100 Pro smartphone model V2324A. The Vivo X100 Pro smartphone is an Android smartphone introduced in November of 2023 and is powered by the MediaTek MT6989 Dimensity 9300 octal-core processor. The MediaTek MT6989W Dimensity 9300 is packaged in a package-on-package (PoP) flip chip ball grid array (FCBGA) measuring 16.0 mm × 14.1 mm × 0.78 mm, with the MT6989W application processor die flip-chip attached to the underlying printed wiring board (PWB).
The MediaTek AHJ11236C die was fabricated on 300 mm wafers using TSMC 4 nm N4P CMOS finFET process, employing high-k metal gate (HKMG) finFET transistors and 14 levels of metallization, including one level of aluminum (Al) and 13 levels of copper (Cu). A two-level contact is used to contact the source/drain (S/D) to metal 0 (M0), consisting of a first-level contact to S/D (CT) and a second level via contact (VCT) from M0 to CT. The gates are contacted with via contacts from M0 (VCG). Logic blocks use 6-track high-density (HD) cells, with a standard cell height of 204 nm.
