Unveiling the Logic Advanced Packaging Briefing

Three times a year we assemble a collection of important updates, supplementary analysis of recent reports, high-level packaging process flows, and sneak peeks at upcoming devices and packaging reports. The result is an Advanced Packaging Analyst’s Briefing, and this year it has a new video format, the first of which has just been published and is available on-demand to our subscribers. In addition to the narrated video presentation, the Analyst’s Briefing is available as a slide presentation with accompanying transcript.

This inaugural Advanced Packaging video briefing introduces three new technology nodes with planned coverage in upcoming reports. The nodes span packaging technologies from industry leaders TSMC, Intel, and Samsung. Samsung’s iCube 2.5D silicon interposer-based heterogenous integration technology is one of those technologies and has been on our analysis roadmap for ages. Now, armed with a sample device, a report detailing this competitor to TSMC’s wildly successful chip-on-wafer-on-substrate (CoWoS) is in the works.

In addition, subscribers will see a narrated comparison between the relative thermal performance of Google’s Tensor G3 fabricated using Samsung’s fanout panel level packaging (FO-PLP) technology and other popular package-on-package (PoP) architectures. The integrated fanout PoP (InFO-PoP) at the heart of Apple’s latest Series 9 Watch is also dissected based on our reverse engineering, with a reconstructed process flow and in-depth look at the packaging centric reasons for including a second functional die in the bottom package of the PoP. Finally, an introduction to Intel’s fully integrated voltage regulator (FIVR) system as found in the Xeon CPU Max 9462 is provided as additional context to our report on the same device.

Go try the new format and stay for the content. Advanced packaging continues to be a key tool enabling next generation performance and the Analyst’s Briefings are a great way to stay in the know.