The back end of line (BEOL) is the part of chip fabrication where individual devices (resistors, capacitors, transistors, etc.) are wired to the wafer. Advancements in far-BEOL interconnect technologies have continued to increase connection densities over the past decade. Further improvements will be enabled through hybrid bonding.

A preview of the topics that will be discussed:

Advanced Logic

• First saw Chip on Wafer (CoW) hybrid bonding technology in the AMD Ryzen 7.
• Stacking memory directly with the processor greatly increases available cache memory.
• Milestone for system-technology-co-optimization (heterogeneous 3D scaling) described in the International Roadmap for Devices and Systems (IRDS) More Moore roadmap.

Image Sensors

• We have seen Wafer-to-Wafer (W2W) stacking since 2016 from Sony.
• Bond pitches as small as 2.2 µm are common, and the trend points to pitches as small as 1.4 μm.
• Direct bond interconnect will ultimately enable digital pixel with in-pixel ADC and stacking of three or more wafers.

Memory

• Hybrid bonding often used in High Bandwidth Memory (HBM) and 3D Xtacking applications.
• Hybrid bonding will be one of most important high density memory enablers.
• Further scaling, greater cost effectiveness, fewer defects, and solutions to thermal issues are still required.

Several of the contributors will be available for the live Q&A session, which will immediately follow the pre-recorded webinar presentation.

Contributors to this presentation include:

• Yuzo Fukuzaki, Alain Gauthier, Eugene Hsu - Logic
• Ziad Shukri, Wilson Machado, Eric Rutulis – Image Sensors
• Jeongdong Choe, Chi Lim Tan – Memory
• Narrated by Taylor St. Germain