Intel i3-8121U Cannon Lake Intel 10 nm SoC Overhead Layout Analysis DDR I/O to CPU Transition Region Standard Cell Essentials

Product Code

SCE-1805-801

Release Date

21/11/2018

Availability

Published

Product Item Code

INT-i3-8121U_die

Device Manufacturer

Intel

Device Type

Microprocessor

Subscription

Compute

Channel

Logic - SoC Design Analysis (IP)

Logic - SoC Design Analysis

Intel i3-8121U Cannon Lake Intel 10 nm SoC Overhead Layout Analysis DDR I/O to CPU Transition Region Standard Cell Essentials

This project presents a Standard Cell Essentials Analysis of the Intel Cannon Lake i3-8121U DDR I/O region. It is a collection of scanning electron microscopy (SEM) montage images showing transition regions between an I/O IP block and a digital logic block, showcasing dummy structures and relationship to system-on-chip (SoC) design rules used on Intel Cannon Lake i3-8121U. The report includes:

Downstream product features and system-on-chip (SoC) level areas of analysis
Technology node contact and back end of line (BEOL) process architecture assessment with stack-up dimensions
Features and dummy structures of the SoC design overhead associated with the transition between design IP blocks
Scanning electron microscope (SEM) montage image of the analyzed bevel areas delivered in CircuitVision
Target areas are typically transitions between different types of IP blocks, such as analog I/O to digital, or to memory, and typically contain many dummy features

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