Sony ISP from 1.12 μm Pixel Pitch, 48 MP, Stacked Back-Illuminated CMOS Image Sensor (Sony Xperia 1 V 5G) Advanced Floorplan Analysis
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This report presents an image signal processor advanced floorplan analysis (ISP) of the Sony ISP from 1.12 μm Pixel Pitch, 48 MP, Stacked Back-Illuminated CMOS Image Sensor, extracted from the Sony Xperia 1 V 5G rear-facing wide-angle camera. The first stacked CMOS image sensor technology with 2-Layer Transistor Pixel (ExmorT), PD, TG, FD on CIS layer, TST, SF, SEL in ISP. The new architecture approximately doubles saturation signal level, reduces noise, and improves dynamic range.
