NVIDIA Blackwell B200 High Performance Interconnect and Packaging Analysis
2 Min Read March 5, 2025
Explore the advanced packaging and architecture of the NVIDIA GB100, featuring dual GPU dies, HBM3E memory, and TSMC's bridge-based CoWoS-L technology—marking a shift in NVIDIA's AI hardware design.
The NVIDIA GB100 analyzed in this report was removed from an NVIDIA HGX B200 accelerator cluster found in a Supermicro SYS-A22GA-NBRT GPU SuperServer. It features two near-reticle sized GPU dies and eight SK hynix high bandwidth memory 3 extended (HBM3E), all integrated using TSMC's lated bridge based packaging technology.
The NVIDIA GB100 leverages TSMC's chip on wafer on substrate (CoWoS) 2.5D packaging technology. However, unlike previous generations of AI hardware from NVIDIA, it utilizes the local area silicon interconnect (-L) variant of CoWoS instead of a monolithic silicon interposer (-S). This marks NVIDIA's first use of a bridge-based 2.5D integration technology.
