This report presents key DC electrical characteristics for peripheral NMOS and PMOS transistors located in the I/O region of the Micron Technology MT40A1G8SA-062E DDR4 SDRAM. The MT40A1G8SA-062E is a high-speed DRAM that uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core, and two corresponding n-bit wide and one-half-clock-cycle data transfers at the I/O pins.