Dr. Jeongdong Choe
Specialities: NAND & DRAM Memory, Emerging Memory.
Jeongdong Choe has a Ph.D. in electronic engineering and 30 years’ experience in semiconductor process integration for DRAM, (V) NAND, SRAM, and logic devices. A Ph.D. in Electronics (Semiconductor) from Sungkyunkwan University, he also holds master’s and bachelor’s Degrees in Materials Engineering (Metallurgical) from Yonsei University. His background includes positions as a Team Lead in R&D for SK-Hynix and Samsung, where he optimized process and device architectures with state-of-the-art technologies for mass production.
At TechInsights he has been focusing on technology analysis on semiconductor process, device, and architecture. He has authored numerous articles on memory technology including DRAM Technology Trends, 2D and 3D NAND Process/Device Integration Details, and Emerging Memory such as STT-MRAM, XPoint, ReRAM and FeRAM Design and Architecture. He quarterly produces and updates a widely distributed memory roadmap on DRAM, NAND, and Emerging Memory.
Jeongdong has over 100 filed/issued patents in semiconductor process integration for DRAM, (V)NAND, SRAM, and logic devices.
Blogs
KIOXIA/WD BiCS8 218L CBA 3D TLC NAND
Discover the latest Hybrid Bonding technology with the KIOXIA/WD BiCS8 CBA 3D TLC NAND. Analyzed by TechInsights, this innovative device showcases an advanced edge-XDEC floor plan and a sophisticated 2-deck integration.
Gain exclusive access to TechInsights' comprehensive 3D NAND Technology Roadmap, guiding you through the ever-evolving landscape of innovation.
Maximizing NAND Capacity per Wafer in 3D NAND Production
Stay ahead in the dynamic world of semiconductor technology with insights into the race for maximum NAND capacity per wafer in 3D NAND production. Discover how advancements are driving innovation, pushing boundaries, and shaping the future of storage.